This invention relates to techniques for testing semiconductor integrated circuit (IC) devices, and more specifically to testing wire bonded IC devices.
Electrical testing of IC devices is a significant component of the cost of the final IC product. Considerable development and test tool investment is made in this aspect of IC manufacture. In Multi-Chip-Module (MCM) packaging, the test strategy is especially critical. Testing the final product, the conventional approach generally favored from the standpoint of both cost and reliability, is not optimum for MCM products since the final yield is a multiple of the yield for each individual die in the MCM package. For example, if each of the dies in the package has a yield of 95%, an MCM with 3 dies will have a yield of only 85.7%. Thus in some IC device packaging, notably MCM packaging, it becomes important to fully test the dies before assembly to identify the Known Good Dies (KGD). This typically involves both electrical functionality tests, and aging or burn-in tests. Burn-in tests are especially important for memory dies, which typically exhibit a 1-5% burn-in failure rate over dies that have been only functionally tested. However, burn-in tests require robust and reliable electrical probe connections. Consequently, it has been the pattern, where devices are mounted using solder bumps, to apply the solder bumps to the device, and employ special testing apparatus that electrically connects to the solder bumps. An example of one of several test approaches that can be used is described and claimed in my co-pending application Ser. No. 09/366,388, filed Aug. 3, 1999, which is incorporated herein by reference, is the use of a silicon test bed in which a pattern of recesses or sockets is etched into a silicon wafer, and the recesses are interconnected to a test circuit that simulates the device circuit. The layout of recesses is made to accommodate the solder ball array on the IC device. The use of silicon as the test bed offers the advantages of high planarity, thermal properties that match the IC substrate, notably coefficient of thermal expansion, and the availability of a well developed interconnect technology for fabricating the test circuit. This test approach and test apparatus works well with IC chips or MCMs that are solder bump mounted, and have an array of solder bumps accessible for testing, but it appears inconsistent with IC devices that are packaged using wire bonds and have only pads accessible. Wire bond interconnections for integrated circuit devices have been widely used in IC packaging because they are relatively inexpensive and are highly reliable. However, burn-in testing IC devices after wire bonding is done in the final package and the die cannot be used for MCMs, and burn-in testing the dies before wire bonding using bare bonding pads is relatively ineffective. A state-of-the-art high pin count wire bonded IC package that avoids this problem is described and claimed in my co-pending application Ser. No. 09/361,100, filed Jul. 1, 1999, which is incorporated herein by reference. This package uses an intermediate interconnection substrate (IIS) and the IC dies are bump mounted on the IIS. However, many IC packages still have IC dies that are directly wire bonded to the next interconnection level. It would be desirable to have a test procedure for burn-in testing of these IC dies that has the effectiveness and process integration compatibility of the bum-in test for bump-bonded devices.
I have developed an IC testing approach for IC dies with wire bond pads that allows effective mounting of the dies for burn-in testing, and thereafter allows interconnection of these dies to the next board level using wire bonds. The wire bond pads are re-routed to bump-bond sites and the dies are provided with bump-bonds for the burn-in test. After test the KGD are packaged using either bump bonds or wire bonds, and can be mounted either face down for bump-bonding or face up for wire bonding.